Conventionally, circuit carriers provide physical housings for integrated circuits and include a set of pins provided along the side or bottom of each carrier for interfacing the integrated circuit to an external environment. Each integrated circuit performs a specific function, such as processing or storage, and the integrated circuit and carrier combinations are generally generically termed chips. The individual carrier pins typically interconnect to a circuit board bus defining a shared electrical pathway for exchanging address, data and control signals with other components, such as individual processors, memories and input-output (I/O) devices. The complexity of a bus architecture increases exponentially with the number of carriers and address, data and control lines involved.
Asserting signals onto and receiving signals from a bus can be expensive in terms of mechanical, electrical and timing design considerations. For instance, propagating signals off-chip can tax the power budget allotted to each chip. Moreover, signal propagation between chips is slower over the bus in comparison to on-chip signal propagation, which can create a lower bound on inter-chip timing. Furthermore, bus skew, caused by signals on different bus lines traveling at different speeds, can further increase signal propagation delay.
Bypassing the conventional bus-based chip interconnection approach, chip-to-chip input/output (I/O) provides direct signal pathways between carriers. Chip-to-chip I/O simplifies routing through direct and immediate electrical pathways, proceeding from one chip directly to the next chip. Consequently, circuit board layout using chip-to-chip I/O requires arranging a matrix of functionally-defined carriers in an edge-to-edge topology. However, although more direct, through-chip hops can form bottlenecks in intermediate chips, particularly if the transient signal traffic is high in a few concentrated chips.
Cornered chip-to-chip I/O is a variation of chip-to-chip I/O that places the input/output signal connectors on the corners of each carrier. Cornered I/O allows increased spacing between the carriers to facilitate chip cooling, chip removal and installation, and eased troubleshooting. The borders of each carrier layout remain conventional square or rectangular designs with the edges of the individual carriers oriented parallel to the edges of each layout. With cornered VO, spacing between adjacent rows and columns of carriers located along the edges of the layout remains unused and can form “holes.” As a result, fewer potential connections are available along the borders with respect to those carriers located in either a corner or along a side of the layout. Connectivity is thereby reduced and overall robustness suffers due to a decreased number of available alternative pathways. Moreover, as carriers located in the corners provide only a single chip-to-chip I/O pathway, a potential single point of failure is formed. As well, two routes between each peer carrier cannot be guaranteed and a layout can suffer non-attainable neighbors.
Therefore, there is a need for an approach to providing an efficient topological layout of cornered chip-to-chip I/O carriers such that inter-chip routing is strengthened through alternate pathways and redundancy. Preferably, such an approach would increase the symmetry, homogeneity and density of routing of chips while minimizing unused space.
There is further need for an approach to providing highly interconnectable carrier layouts with a rich set of potential interfaces. Preferably, such an approach would facilitate building interconnected matrixes of functionally-defined carrier layouts configured in one or more layers.